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APL5330
Dual Input 2A Low Dropout Regulator
Features
* *
Fast Transient Response High Output Accuracy - 20mV over Load, Output Voltage Offset and Temperature
General Description
The APL5330 integrates a power transistor to provide regulated voltage with maximum output current of 2A. It also incorporates current-limit, thermal shutdown and shutdown control functions into a single chip. The current-limit circuit limits the maximum output current in overload or short-circuit conditions. The on-chip thermal shutdown provides protection against any combination of overload that would create excessive junction temperature. The output voltage of the APL5330 tracks the reference voltage on VREF pin. A resistor divider connected to VREF pin is usually used to provide reference voltage to the IC. In addition, an external ceramic capacitor and an open-drain transistor connected to VREF pin provides soft-start and shutdown control. Applying and holding a voltage below 0.35V (typ.) to VREF shuts off the output.
* * * * * *
Adjustable Output Voltage by External Resistors Current-Limit Protection On-Chip Thermal Shutdown Shutdown for Standby or Suspend Mode Simple SOP-8 and SOP-8 with Thermal Pad Packages Lead Free Available (RoHS Compliant)
Applications
* *
VGA Card Power Chip Set Power
Pin Configuration
VIN GND VREF VOUT 1 2 3 4 8 7 6 5 VCNTL VCNTL VCNTL VCNTL VIN GND VREF VOUT 1 2 3 4 8 7 6 5 NC NC VCNTL NC
SOP-8 (Top View) NC = No internal connection = Thermal Pad
SOP-8-P (Top View)
(connected to GND plane for better heat dissipation)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 1 www.anpec.com.tw
APL5330
Ordering and Marking Information
APL5330 Lead Free Code Handling Code Temp. Range Package Code APL5330KE-TR : APL5330KAE-TR : APL5330 XXXXX Package Code K : SOP-8 KA : SOP-8-P Operating Ambient Temp. Range E : -20 to 70 C Handling Code TR : Tape & Reel Lead Free Code L : Lead Free Device Blank : Original Device XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature.
Pin Description
PIN NAME VIN GND VCNTL I/O I O I DESCRIPTION Main power input pin. Connect this pin to a voltage source and an input capacitor. The APL5330 provides current from VIN pin to VOUT pin by controlling the NPN pass transistor. Signal ground. Power input pin for internal control circuitry. Connect this pin to a voltage source to provide a bias for the internal control circuitry. A bypass capacitor is usually connected near this pin. Reference voltage input and active-low shutdown control pin. Connect this pin to a resistor divider and a capacitor for soft-start and filtering noise purposes. Pulling and holding the voltage on this pin low by an open-drain transistor shuts down the output. Output pin of the regulator. Connect this pin to load. Output capacitors connected to this pin improves stability and transient response. The output voltage tracks the reference voltage, and the output pin provides the maximum current up to 2A.
VREF
I
VOUT
O
Block Diagram
VCNTL VIN
VREF
Voltage Regulation
Thermal Limit
Current Limit
VOUT
Shutdown GND
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APL5330
Absolute Maximum Ratings
Symbol VCNTL VIN PD TJ TSTG TSDR VESD Parameter VCNTL Supply Voltage, VCNTL to GND VIN Supply Voltage, VIN to GND Power Dissipation Junction Temperature Storage Temperature Soldering Temperature, 10 Seconds Minimum ESD Rating (Human Body Mode) Rating -0.2 ~ 7 -0.2 ~ 3.9 Internally Limited 150 -65 ~ 150 300 3 Unit V V W
o o o
C C C
kV
Thermal Characteristics
Symbol JA JC Parameter Junction-to-Ambient Thermal Resistance in Free Air SOP-8 SOP-8-P Junction-to-Case Thermal Resistance SOP-8 SOP-8-P Value 75 55 28 20 Unit
o
C/W
o
C/W
Note : JA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of SOP-8-P is soldered directly on the PCB.
Recommended Operating Conditions
Symbol VCNTL VIN VREF VOUT IOUT TJ Parameter VCNTL Supply Voltage (Note 1) VIN Supply Voltage (Note 2) VREF Input Voltage VOUT Output Voltage (Note 3) VOUT Output Current (Note 4) Junction Temperature Range 3.1 ~ 6 1.2 ~ 3.5 0.8 ~ 3 VREF 0.02 2 -20 ~ 125 Unit V V V V A
o
C
Notes : 1. Please refer to the VCNTL-to-Vin Dropout Voltage in the "Typical Characteristics" section for the minimun supply voltage on VCNTL. 2. Please supply enough voltage to VIN for providing desired maximum output current. Please refer to the VIN. Dropout Voltage vs Output Current in the Typical Characteristics. 3. The VOUT is regulated to the VREF with additional voltage offset and load regulation except over-load conditions. 4. The maximum IOUT varies with the TJ and the voltages of VIN-VOUT and VOUT.
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APL5330
Electrical Characteristics
Refer to the typical application circuit. These specifications apply over VCNTL = 3.3V, VIN = 2V, VREF = 1.2V and TA = -20 to 70C, unless otherwise specified. Typical values are at TA = 25C.
Symbol
Parameter
Test Conditions
APL5330 Min Typ VREF -20 -8 -3 0.47 0.7 20 Max
Unit
OUTPUT VOLTAGE VOUT VOUT Output Voltage System Accuracy Load Regulation VIN Dropout Voltage PROTECTION ILIM TSD Current Limit Thermal Shutdown Rising TJ Temperature Thermal Shutdown Hysteresis IOUT = 0A ICNTL VCNTL Supply Current IOUT = 2A (Normal Operation) VREF = GND (Shutdown) IVREF Normal operation VREF Bias Current (The current flows out of VREF) VREF = GND (Shutdown) Shutdown Voltage Threshold 0.2 0.5 TJ = 25C TJ = 125C 2.4 2.7 2.6 170 30 2 25 0.3 150 300 0.35 500 5000 0.65 nA 4 50 mA A
o o
IOUT = 0A Over temperature, VOUT offset, and load regulation IOUT = 10mA to 2A IOUT = 2A
V mV mV V
C C
INPUT CURRENT
SHUTDOWN CONTROL V
Typical Application Circuit
VCNTL +3.3V VIN +2V
VIN VCNTL
R1 3.5k
VREF
VREF GND VOUT
VOUT 1.2V/2A COUT 330uF
Shutdown R2 2k GND CSS 0.1uF
CIN 47uF
CCNTL 1uF
GND
VOUT = VREFIN
R2 (V) R1 + R2
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APL5330
Typical Characteristics
Current-Limit vs. Junction Temperature
3.5
VIN = 2V
2500
Quiescent VCNTL Current vs. Junction Temperature Quiescent VCNTL Current, ICNTL (A)
IOUT= 0A
2000
3
VOUT=1.2V
Current-Limit, ILIM (A)
2.5 2 1.5 1 0.5 0 -50
VCNTL = 5V
VCNTL = 3.3V
1500
VCNTL = 5V VCNTL = 3.3V
1000
500
-25
0
25
50
75
100
125
0 -50
-25
0
25
50
75
100
125
Junction Temperature (C)
Junction Temperature (C)
VREF Threshold Voltage vs. Junction Temperature
0.6
VCNTL = 5V
VREF Bias Current vs. VREF Supply Voltage
500
VREF Bias Current, IVREF (nA)
VREF Threshold Voltage (V)
450 400 350 300 250 200 150 100 50 0 0 0.5 1 1.5 2 2.5 3
0.5 0.4 0.3 0.2 0.1 0 -50 -25 0 25 50 75 100 125
VCNTL = 3.3V
VCNTL= 3.3V VCNTL= 5V
Junction Temperature (C)
VREF Supply Voltage (V)
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APL5330
Typical Characteristics (Cont.)
VIN Dropout Voltage vs. Output Current
0.6
VIN Dropout Voltage vs. Output Current
0.6
VCNTL = 5V
VCNTL = 3.3V
0.5
VREF = 1.2V
TJ = 125oC
0.5
VREF = 1.2V TJ = 125oC
VIN Dropout Voltage (V)
VIN Dropout Voltage (V)
0.4
TJ = 75oC
0.4
TJ = 75oC
0.3
0.3
TJ = -25oC
TJ = 25oC
0.2
0.2 0.1 0
TJ = 25oC
TJ = -25oC
0.1
0 0 0.5 1 1.5 2
0
P.6 kWI 0.5 1 1.5
Output Current (A)
2
Output Current (A)
VCNTL Input Current vs. VIN - VOUT Voltage at IOUT=1A Minimum VCNTL - VOUT Voltage (V)
140
3.8
VCNTL-to-VOUT Dropout Voltage vs. VCNTL Input Current
IOUT = 1A
VCNTL Input Current, ICNTL (mA)
IOUT = 1A
120 100 80 60 40 20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
TJ = 25oC TJ = -25oC TJ = 125oC TJ = 75oC
3.4 3 2.6 2.2 1.8 1.4 1 0 20
TJ = 75oC
TJ = 25oC TJ = -25oC TJ = 125oC
40
60
80
100
120
VIN - VOUT Voltage (V)
VCNTL Input Current, ICNTL (mA)
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APL5330
Typical Characteristics (Cont.)
VCNTL Input Current vs. VIN - VOUT Voltage at IOUT=1.5A VCNTL Input Current, ICNTL (mA)
IOUT = 1.5A
VCNTL-to-VOUT Dropout Voltage vs. VCNTL Input Current Minimum VCNTL - VOUT Voltage (V)
3.8
IOUT = 1.5A
140 120 100 80 60
TJ = 25oC
3.4 3 2.6 2.2 1.8 1.4
TJ = 75oC TJ = -25oC TJ = 125oC TJ = 25oC
TJ = 125oC TJ = 75oC
40 20 0 0.3 0.4 0.5 0.6 0.7 0.8
TJ = -25oC
1 0 20 40 60 80 100 120
0.9
1
1.1
VIN - VOUT Voltage (V)
VCNTL Input Current, ICNTL (mA)
VCNTL Input Current vs. VIN - VOUT Voltage at IOUT=2A VCNTL Input Current, ICNTL (mA)
IOUT = 2A
VCNTL-to-VOUT Dropout Voltage vs. VCNTL Input Current Minimum VCNTL - VOUT Voltage (V)
3.8
IOUT = 2A
140 120 100 80
TJ = 125oC TJ = 25oC TJ = 75oC
3.4 3 2.6 2.2 1.8 1.4 1 0 20 40 60 80 100 120
TJ = 125oC TJ = 75oC TJ = 25oC TJ = -25oC
60 40 20 0 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2
TJ = -25oC
VIN - VOUT Voltage (V)
VCNTL Input Current, ICNTL (mA)
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APL5330
Operating Waveforms
1. Load Transient Response : IOUT = 10mA -> 2A -> 10mA - VIN = 2V, VCNTL = 3.3V, VOUT = 1.2V - VREF is 1.2V supplied by a regulator - COUT = 330F, ESR = 14m - IOUT slew rate = 2A/s
Load Regulation = -2.8mV
V OUT
1
V OUT
V OUT
1
1
IOUT
IOUT
2A
IOUT
2
10mA
2
2
Ch1 : VOUT, 20mV/Div, AC Ch2 : IOUT, 1A/Div Time : 1s/Div
Ch1 : VOUT, 20mV/Div, AC Ch2 : IOUT, 1A/Div Time : 10s/Div
Ch1 : VOUT, 20mV/Div, AC Ch2 : IOUT, 1A/Div Time : 1s/Div
2. Short-Circuit Test - VIN = 2V, VCNTL = 3.3V, VOUT = 1.2V VOUT is Shorted to GND VOUT is Shorted to GND
V OUT
1
V OUT
1
IOUT IOUT
2 2
Ch1 : VOUT, 1V/Div, DC Ch2 : IOUT, 2A/Div Time : 50s/Div
Ch1 : VOUT, 1V/Div, DC Ch2 : IOUT, 2A/Div Time : 50ms/Div
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APL5330
Operating Waveforms (Cont.)
3. Power on/off - VIN = 2V, VCNTL = 3.3V, VOUT = 1.2V
V IN V IN
1 1
V OUT
2
V OUT
2
IOUT IOUT
3 3
Ch1 : VIN, 1V/Div, DC Ch2 : VOUT, 1V/Div, DC Ch3 : IOUT, 1A/Div Time : 1ms/Div
Ch1 : VIN, 1V/Div, DC Ch2 : VOUT, 1V/Div, DC Ch3 : IOUT, 1A/Div Time : 10ms/Div
4. Enable/Shutdown - VIN = 2V, VCNTL = 3.3V, VOUT = 1.2V
VREF
1
VREF
1
V OUT
2
V OUT
2
IOUT
3
IOUT
3
Ch1 : VREF, 1V/Div, DC Ch2 : VOUT, 1V/Div, DC Ch3 : IOUT, 1A/Div Time : 2ms/Div
Ch1 : VREF, 1V/Div, DC Ch2 : VOUT, 1V/Div, DC Ch3 : IOUT, 1A/Div Time : 2ms/Div
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APL5330
Application Information
General The APL5330 is a linear regulator and is capable of providing output current up to 2A. The APL5330 is designed with the fast transient response, accurate output voltage, active-low shutdown control and fault protections (current-limit, thermal shutdown). The APL5330 is available in two packages to meet wide range of power dissipation requirements in various applications. Output Voltage Regulation The output voltage on VOUT pin tracks the reference voltage on VREF pin. A bypass NPN transistor controlled by a high bandwidth error amplifier regulates the output voltage by providing output current from VIN pin to the output. The base current of the pass transistor is provided by the VCNTL pin. An internal kelvin sensing scheme is used at the VOUT pin for perfect load regulation. Since the APL5330 exhibits very fast load transient response, lesser amount of capacitors can be used. Current Limit The APL5330 monitors the output current, and limits the maximum output current to prevent damages during overload or short-circuit conditions. To increase the input voltage on VIN or VCNTL will get higher current-limit points. Shutdown and Soft-Start The VREF pin is a dual-function input pin, acting as reference input and shutdown control input. Applying and holding a voltage below 0.35V(typ.) to VREF pin shuts down the output of the regulator. An NPN transistor or N-channel MOSFET is normaly used to pull down the VREF voltage while applying a "high" signal to turn on the transistor. When release the VREF pin, the current through the resistor divider charges the soft-start capacitor to initiate a soft-start process. The output voltage tracks the VREF voltage rises. The soft start function limits the input current. Thermal Shutdown A thermal shutdown circuit limits the junction temperature of the APL5330. When the junction temperature exceeds TJ= +170oC, a thermal sensor turns off the bypass transistor, allowing the device to cool down. The regulator starts to regulate again after the junction temperature reduces by 30oC, resulting in a pulsed output during continuous thermal overload conditions. The thermal limit designed with a 30oC hysteresis lowers the average TJ during continuous thermal overload conditions to extend life time of the APL5330. Power Inputs Input power sequencing is not necessary for VIN and VCNTL voltage supplies. However, do not apply a voltage to VOUT when there is no VCNTL voltage. This is because the internal parasitic diodes connected from VOUT to VIN or VCNTL is forward bias. The APL5330 can supply few current to load when the input voltage on VIN is not present. Reference Voltage The reference voltage is applied to the VREF pin connected with a resistor divider. Normally the bias current of the VREF pin flows out of the IC and is about 150nA (typ.), creating a voltage offset to the resistor divider and affecting the output voltage accuracy. The recommended resistors are <5k to maintain the accurate output voltage. An external bypass capacitor is also connected to VREF. The capacitor (>0.1F) and the resistor divider form a low-pass filter to reduce the inherent reference noise. Connect the capacitor as close to VREF as possible for optimal effect. More capacitance and large resistor divider will increase the soft-start interval. Do not place any additional loading on this reference input pin.
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APL5330
Application Information (Cont.)
Output Capacitor The APL5330 requires a proper output capacitor to maintain stability and improve transient response. The APL5330 can work stably with wide range of capacitance and ESR (equivalent series resistance). A low-ESR solid tantalum, aluminum electrolytic or ceramic output capacitor works extremely well and provides good transient response and stability over temperature. The output capacitors also reduce the slew rate of load current and help the APL5330 to minimize variations of the output voltage. For this purpose, the low-ESR capacitors which depend on the step size and slew rate of load current are recommended.
25
For VCNTL pin, a capacitor of 1F (ceramic chip capacitor) or greater (aluminum electrolytic capacitor) is recommended. For VIN pin, an aluminum electrolytic capacitor (>47F) is recommended. It is not necessary to use low-ESR capacitors. Layout and Thermal Consideration The input capacitors for VIN and VCNTL pins are normally placed near each pin for good performances. Ceramic decoupling capacitors of output must be placed as close to the load to reduce the parasitic inductance of traces. It is also recommended to place the APL5330 and output capacitors near the load for good load regulation and load transient response. Please connect the negative pins of the input and output capacitors and the GND pin of the APL5330 to the power ground plane of the load.
20
See figure 1. The SOP-8-P utilizes a bottom thermal pad to minimize the thermal resistance of the package
Stable Region
ESR (m [ )
15
and make the package suitable for high current applications. The thermal pad is soldered to the top ground pad connected to the internal or bottom ground plane by several vias. The printed circuit board (PCB) forms a heat sink and dissipates most of the heat into ambient air. It is recommended that the vias have proper size to retain solder and help heat conduction. Thermal resistance consists of two main elements, JC (junction-to-case thermal resistance) and CA (case-to-ambient thermal resistance). JC is specified from the IC junction to the bottom of the thermal pad directly below the die. CA is the resistance from the bottom of thermal pad to the ambient air and it includes CS (case-to-sink thermal resistance) and SA (sink-toambient thermal resistance). The specified path for heat flow is the lowest resistance path and it dissipates majority of the heat to the ambient air. Typically, CA is the dominant thermal resistance. Therefore, enlarging
10
5
0 10 100 1000
Capacitance (uF)
Input Capacitor The input capacitors of VCNTL and VIN pins are not required for stability but for supplying surge current during large load transients. This will prevent the input rail from dropping and improve the performance of the APL5330. The parasitic inductors between voltage sources or bulk capacitors and the power input pins will limit the slew rate of the surge currents during large load transients, resulting in voltage drop at VIN and VCNTL pins.
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APL5330
Application Information (Cont.)
Layout and Thermal Consideration (Cont.) the internal or bottom ground plane reduces the resistance CA . The relationship between power di s s ipa tio n and temperatures is the following equation: PD = (TJ - TA) / JA where, PD : Power dissipation TJ : Junction Temperature TA : Ambient Temperature JA : Junction-to-Ambient Thermal Resistance
102 mil
118 mil
SOP-8-P
Die
Thermal pad
Top ground pad
Ambient Air
Vias
Internal Printed g r o u n d circuit plane board
Figure 1 Top and side view of layout around the APL5330
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APL5330
Packaging Information
SOP-8 pin (Reference JEDEC Registration MS-012)
E
H
e1
e2
D
A1
A
1
0.015X45
L 0.004max.
Dim A A1 D E H L e1 e2 1
Millimeters Min. 1.35 0.10 4.80 3.80 5.80 0.40 0.33 1.27BSC 0 8 0 Max. 1.75 0.25 5.00 4.00 6.20 1.27 0.51 Min. 0.053 0.004 0.189 0.150 0.228 0.016 0.013
Inches Max. 0.069 0.010 0.197 0.157 0.244 0.050 0.020 0.50BSC 8
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APL5330
Packaging Information
SOP-8-P pin ( Reference JEDEC Registration MS-012)
E1 D1
E
H
e1 D
e2
A1
A
1 L
0.004max.
Dim A A1 D D1 E E1 H L e1 e2 1
Millimeters Min. 1.35 0 4.80 3.00REF 3.80 2.60REF 5.80 0.40 0.33 1.27BSC 8 6.20 1.27 0.51 0.228 0.016 0.013 4.00 0.150 Max. 1.75 0.15 5.00 Min. 0.053 0 0.189
0.015X45
Inches Max. 0.069 0.006 0.197 0.118REF 0.157 0.102REF 0.244 0.050 0.020 0.50BSC 8
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APL5330
Physical Specifications
Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
TP
(IR/Convection or VPR Reflow)
tp Critical Zone T L to T P
Ramp-up
Temperature
TL Tsmax
tL
Tsmin Ramp-down ts Preheat
25
t 25 C to Peak
Tim e
Classification Reflow Profiles
Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classificatioon Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly 3C/second max. 100C 150C 60-120 seconds 183C 60-150 seconds See table 1 10-30 seconds Pb-Free Assembly 3C/second max. 150C 200C 60-180 seconds 217C 60-150 seconds See table 2 20-40 seconds
6C/second max. 6C/second max. 6 minutes max. 8 minutes max. Time 25C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface.
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APL5330
Classification Reflow Profiles(Cont.)
Table 1. SnPb Entectic Process - Package Peak Reflow Temperatures 3 3 Package Thickness Volum e m m Volume mm <350 350 <2.5 m m 240 +0/-5C 225 +0/-5C 2.5 m m 225 +0/-5C 225 +0/-5C
Table 2. Pb-free Process - Package Classification Reflow Temperatures 3 3 3 Package Thickness Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 m m 260 +0C* 260 +0C* 260 +0C* 1.6 m m - 2.5 m m 260 +0C* 250 +0C* 245 +0C* 2.5 m m 250 +0C* 245 +0C* 245 +0C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0C. For example 260C+0C) at the rated MSL level.
Reliability Test Program
Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245C, 5 SEC 1000 Hrs Bias @125C 168 Hrs, 100%RH, 121C -65C~150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1 tr > 100mA
Carrier Tape
t P P1 D Po E
F W
Bo
Ao
Ko D1
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APL5330
Carrier Tape(Cont.)
T2
J C A B
T1
Application SOP- 8/ SOP-8-P
A 330 1 F 5.5 1
B 62 +1.5 D
C 12.75+ 0.15 D1
J 2 0.5 Po 4.0 0.1
T1 12.4 0.2 P1 2.0 0.1
T2 2 0.2 Ao 6.4 0.1
W 12 0. 3 Bo 5.2 0. 1
P 8 0.1 Ko
E 1.750.1 t
1.55 +0.1 1.55+ 0.25
2.1 0.1 0.30.013
(mm)
Cover Tape Dimensions
Application SOP- 8 / SOP-8-P Carrier Width 12 Cover Tape Width 9.3 Devices Per Reel 2500
Customer Service
Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369
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